United Microelectronics Company, a worldwide semiconductor foundry, and Cadence Design Techniques, Inc. has introduced that Cadence 3D-IC reference movement, that includes the Integrity 3D-IC Platform, has been licensed for UMC’s chip stacking applied sciences, enabling sooner time to market.
UMC’s hybrid bonding options are actually able to help the mixing throughout a broad vary of expertise nodes which might be appropriate for edge AI, picture processing, and wi-fi communication functions. Utilizing UMC’s 40nm low energy (40LP) course of as a wafer-on-wafer stacking demonstration, the 2 corporations collaborated to validate key 3D-IC options on this design movement, together with system planning and clever bump creation with Cadence’s Integrity 3D-IC platform, the answer that integrates system planning, chip and packaging implementation, and system evaluation in a single platform.
“Curiosity in 3D-IC options has elevated notably previously 12 months as our clients search methods to spice up design efficiency with out sacrificing space or value,” says Osbert Cheng, vp of gadget expertise improvement & design help at UMC. “Value-effectiveness and design reliability are the pillars of UMC’s hybrid bonding applied sciences, and this collaboration with Cadence offers mutual clients with each, serving to them reap the advantages of 3D constructions whereas additionally accelerating the time wanted to finish their built-in designs.”
“With rising design complexity for IoT, AI, and 5G functions, wafer-on-wafer expertise automation is more and more essential for chip designers,” says Don Chan, vp, R&D within the digital & Signoff Group at Cadence. “The Cadence 3D-IC movement with the Integrity 3D-IC platform is optimised to be used on UMC’s hybrid bonding applied sciences, offering clients with a complete design, verification and implementation answer that permits them to create and confirm modern 3D-IC designs with confidence whereas accelerating time to market.”
The reference movement, that includes Cadence’s Integrity 3D-IC Platform, is constructed round a high-capacity, multi-technology hierarchical database. The platform affords design planning, implementation and evaluation of full 3D designs inside a single, unified cockpit. A number of chiplets in a 3D stack will be designed and analysed collectively by means of built-in early evaluation for thermal, energy and static timing evaluation. The reference movement additionally permits system-level format versus schematic (LVS) checking to connectivity accuracy, electrical rule-checking (ERC) for protection and alignment checking, and thermal evaluation for warmth distribution in a 3D stacked-die design construction.
Along with the Integrity 3D-IC platform, the Cadence 3D-IC movement additionally consists of the Innovus Implementation System, Quantus Extraction Answer, Tempus Timing Signoff Answer, Pegasus Verification System, Voltus IC Energy Integrity Answer and Celsius Thermal Solver for system evaluation.
For extra info, please go to right here.
Touch upon this text beneath or by way of Twitter: @IoTNow_OR @jcIoTnow